LabsLand FPGA Community

DE1-SoC

Learn FPGA design with VHDL, Verilog, or SystemVerilog.

Real-time labs
Codeide
University & College

Laboratory information

Write and compile your design in the browser, then test it on a real DE1-SoC. Observe the LEDs and seven-segment displays through the live camera and interact using the virtual switches and buttons.

To use UART, choose Standard in the interface selector and enable the UART serial terminal before entering. UART sessions use compatible boards.

What students do

Operate real equipment and reason from the measurements.

Recommended level: University & College
Typical access model: Real-time labs, Codeide
Works on: Modern web browsers on school, university, and home computers.
Teaching use: Suitable for assignments, demonstrations, LMS-linked activities, and remote practical work.

Ready lesson plans

Teach lessons using this laboratory

Preview classroom-ready activities that guide students through the real laboratory.

Digital Logic on the DE1-SoC (1/6): Your first gates on real hardware

Students write Verilog for basic logic gates, synthesize and upload to the DE1-SoC, and verify truth tables on real switches and LEDs.

Digital systems & FPGA
Undergraduate, introductory
50 min

Preview lesson

Digital Logic on the DE1-SoC (2/6): Truth tables, SOP/POS, K-maps, and a multiplexer

Students connect truth tables, Boolean forms, Karnaugh maps, and multiplexers, then test minimized combinational logic on DE1-SoC hardware.

Digital systems & FPGA
Undergraduate, introductory
70 min

Preview lesson

Digital Logic on the DE1-SoC (3/6): Memory — flip-flops and registers

Students build D flip-flop and register circuits in Verilog, test clock and reset behavior, and distinguish combinational logic from stored state.

Digital systems & FPGA
Undergraduate, introductory
55 min

Preview lesson

Browse all Teach lessons

Video

Watch video

Available experiments

Use the real laboratory from the browser.

DE1-SoC · Verilog

Write Verilog code in your browser and run it on a real DE1-SoC.

DE1-SoC · VHDL

Write VHDL code in your browser and run it on a real DE1-SoC.

DE1-SoC · SystemVerilog

Write SystemVerilog code in your browser and run it on a real DE1-SoC.

Teaching resources

Public laboratory contents

Adapting external codes

How to adapt external VHDL or Verilog codes or external practices to the LabsLand FPGA laboratory

Open resource

Introduction to LabsLand FPGA. Simple combinational ALU.

Introduction to the LabsLand FPGA laboratory. Activity that involves the design of a combinational ALU that makes simple arithmetical operations.

Through this activity the following goals will be met:

Learn how to use the LabsLand FPGA lab.
Learn how to design entities that are reusable through components and port mapping.
Learn how to use elementary input-output peripherals (switches, buttons, 7-segment displays).
Learn basic combinational system concepts.
Learn how to design a simple ALU, that makes simple airthmetical operations.
Learn how to use "resize", type conversions and other VHDL characteristics.

Open resource

Breadboard GPIO guide

Use the breadboard to map GPIO to switches and LED's

Open resource

RHL Beadle

80+ pages of contents on how to use the FPGA laboratory, Boole Designer, Digital Trainer

Open resource

Introduction to LabsLand FPGA. Simple combinational ALU. (SOLVED).

Introduction to the LabsLand FPGA laboratory. Activity that involves the design of a combinational ALU that makes simple arithmetical operations.

(This is the solved version of this practice. The not-solved version is a different version of this practice).

Through this activity the following goals will be met:

Learn how to use the LabsLand FPGA lab.
Learn how to design entities that are reusable through components and port mapping.
Learn how to use elementary input-output peripherals (switches, buttons, 7-segment displays).
Learn basic combinational system concepts.
Learn how to design a simple ALU, that makes simple airthmetical operations.
Learn how to use "resize", type conversions and other VHDL characteristics.