Nios V for DE1-SoC
Upload an ELF program and run it on the fixed FPGAcademy DE1-SoC Computer with Nios V. Representative hello and switch-to-LED binaries are preloaded.
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LabsLand FPGA Community
Nios V for DE1-SoC
Run Nios V RISC-V programs on a real DE1-SoC board using C, assembly, or direct ELF upload.
- Codeide
- Laboratoires en temps réel
- Université et Collège
Informations du laboratoire
Summary
This lab gives students remote access to a real Terasic DE1-SoC board running the FPGAcademy DE1-SoC Computer with Nios V system. The FPGA bitstream is fixed by LabsLand, so students focus on building or uploading ELF programs for the Nios V RISC-V soft-core processor and observing the result on the live board.
Ways to use the lab
- Nios V for DE1-SoC: upload an existing ELF program and run it on the fixed Nios V system.
- Nios V C IDE for DE1-SoC: write C code in CodeIDE, build a Nios V ELF, and upload it to the board.
- Nios V Assembly IDE for DE1-SoC: write RISC-V assembly in CodeIDE, build a Nios V ELF, and upload it to the board.
Good fit for courses and activities
The lab is useful for introductory and intermediate activities in embedded systems, RISC-V assembly, embedded C, memory-mapped I/O, GPIO programming, JTAG UART output, and soft-core processor workflows on FPGA hardware. Typical exercises include printing messages over the JTAG UART, reading switch inputs, driving LEDs, comparing C and assembly implementations, and uploading instructor-provided ELF binaries.
Hardware and fixed system
The physical target is a Terasic DE1-SoC board with an Intel/Altera Cyclone V SoC FPGA. LabsLand programs the board with the FPGAcademy DE1-SoC Computer with Nios V bitstream before the student ELF is loaded. In this MVP, students do not change the FPGA fabric or upload a custom SOF from these entries; they run firmware on the provided Nios V system.
Switch and LED mapping
The on-screen controls are labelled NSW0 through NSW9. These are logical Nios V switches mapped to the GPIO/JP1 input path used by the fixed FPGAcademy system. The starter and demo programs mirror NSW0..NSW9 to LEDR0..LEDR9, so students can verify their program with the real board camera. The NSW naming is intentional because this Nios V system uses a different remote-control mapping from the generic HDL-mode switch labels.
References
For the processor system, memory map, and I/O details, see the FPGAcademy DE1-SoC Computer with Nios V reference. The lab documentation panel also links this reference from inside each session.
Ce que font les étudiants
Ils pilotent de vrais équipements et raisonnent à partir des mesures.
- Niveau recommandé
- Université et Collège
- Modèle d'accès habituel
- Codeide, Laboratoires en temps réel
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- Usage pédagogique
- Adapté aux devoirs, démonstrations, activités liées au LMS et travaux pratiques distants.
Expériences disponibles
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Nios V C IDE for DE1-SoC
Write C code in CodeIDE, build a Nios V ELF, and run it on a real DE1-SoC configured with the fixed FPGAcademy Nios V system. The default program mirrors NSW0..NSW9 to LEDR0..LEDR9.
Nios V Assembly IDE for DE1-SoC
Write RISC-V assembly in CodeIDE, build a Nios V ELF, and run it on a real DE1-SoC configured with the fixed FPGAcademy Nios V system. The default program mirrors NSW0..NSW9 to LEDR0..LEDR9.