How to design and assess a remote lab assignment: a Boyle’s law example
Design an assessable activity with the Boyle’s law lab: student brief, data table, 20-point rubric and feedback examples.
Month: October 2026
A first remote FPGA assignment in Verilog: from requirement to truth table
Teach a first Verilog assignment on a remote DE1-SoC FPGA with a truth table, simulation-checked code, a student worksheet and a practical marking guide.