LabsLand is a global network of real laboratories available online. Students (in schools, universities and life-long learning platforms) can access the real laboratories through the Internet, using their laptop, tablet or phone.

The laboratories are either real-time (Arduino, FPGAs...) located in different multiple universities all over the world. In certain fields (Physics, Biology, Chemistry) the laboratories are LabsLand Ultraconcurrent Laboratories, so the university has recorded all the potential combinations of what can be done in the laboratory (in some cases, several thousands) and make it available in an interactive way.

In every case, the laboratory is always real (not simulated), and available through the Web (you do not need to obtain any hardware, deal with shipping, etc.).

Check how a typical user session works in the following video:

This laboratory will let you learn basic Digital Electronics.

You will be able to design Combinational Systems by designing and filling a truth table, use Boolean Algebra, create Karnaugh–Veitch (KV or VK) maps, and try the systems that you create in real remote hardware (Intel FPGAs).

Summary

The Digital Trainer laboratory is designed towards students that are starting with digital logic, truth tables and Boole's Algebra.

During the activity, the student sees an Intel FPGA that implements a series of simple truth tables. The student can interact with the FPGA devices to vary the inputs to the system through switches, and observe the outputs through LEDs. The challenge is to determine which logical operator the FPGA implements in each case (e.g. AND, NAND...).

 

Further details

The activity is designed to be relatively simple and straightforward, but at the same time to be engaging for the students. It is designed in a game-like style, and it is based in real hardware (FPGAs). That way, it is not only useful to introduce and obtain familiarity with digital logic, but also it allows students to start seeing the future uses of that knowledge, interacting in a superficial way with FPGA devices, of the same kind that are used in industry.

Interaction with the FPGA devices does not add complexity, since students don't need to program them; they already implement a black box logic (which is precisely the point of the activity).

The laboratory is originally based in an activity that Intel Corporation frequently conducts in its seminars, both hands-on and remote, using their Intel DE1-SoC, Intel DE2-115, or other types of FPGAs.

Learn Hardware design with real FPGAs!

In this laboratory, you can learn how to program using two Hardware Design Languages: VHDL or Verilog, and test your code in one of our multiple boards available. Every FPGA has a set of components already place, such as 10 LEDs, 6 7-segment displays or multiple clocks. In addition, you will have access to 10 virtual switches and 4 virtual buttons that you can use in your design and that you will see when interacting with the real hardware.

Whenever you synthesize your code, you will be assigned to a particular board (such as Terasic DE2-115 or Terasic DE1-SoC or others), and you will be able to send your code to one of the available boards and to turn on and off the switches or press the buttons and see how your design behaves. The boards are located in different universities, as you will see when using each board.

In this laboratory, you do not need any software or hardware installed in your computer, tablet or phone.

Learn Hardware design with FPGAs using Terasic DE1-SoC!

In this laboratory, you can learn how to program using two Hardware Design Languages: VHDL or Verilog, and test your code in a real Terasic DE1-SoC FPGA. The FPGA has a set of components already place, such as 10 red LEDs, 6 7-segment displays or multiple clocks. In addition, you will have access to 10 virtual switches and 4 virtual buttons that you can use in your design and that you will see when interacting with the real hardware. This way, you will be able to turn on and off the switches or press the buttons and see how your design behaves. The boards are located in different universities, as you will see when using each board.

In this laboratory, you do not need any software or hardware installed in your computer, tablet or phone.

Learn Hardware design with FPGAs using Terasic DE1-SoC!

In this laboratory, you can learn how to program using two Hardware Design Languages: VHDL or Verilog, and test your code in a real Terasic DE1-SoC FPGA. The FPGA has a set of components already place, such as 10 red LEDs, 6 7-segment displays or multiple clocks. In addition, you will have access to 10 virtual switches and 4 virtual buttons that you can use in your design and that you will see when interacting with the real hardware. This way, you will be able to turn on and off the switches or press the buttons and see how your design behaves. The boards are located in different universities, as you will see when using each board.

In this laboratory, you do not need any software or hardware installed in your computer, tablet or phone.

Learn Hardware design with FPGAs using Terasic DE2-115!

In this laboratory, you can learn how to program using two Hardware Design Languages: VHDL or Verilog, and test your code in a real Terasic DE2-115 FPGA. The FPGA has a set of components already place, such as 18 red LEDs, 9 green LEDs, 8 7-segment displays, multiple clocks. In addition, you will have access to 18 virtual switches and 4 virtual buttons that you can use in your design and that you will see when interacting with the real hardware. This way, you will be able to turn on and off the switches or press the buttons and see how your design behaves. The boards are located in different universities, as you will see when using each board.

In this laboratory, you do not need any software or hardware installed in your computer, tablet or phone.

Learn Hardware design with FPGAs using Terasic DE2-115!

In this laboratory, you can learn how to program using two Hardware Design Languages: VHDL or Verilog, and test your code in a real Terasic DE2-115 FPGA. The FPGA has a set of components already place, such as LEDs, 7-segment displays or multiple clocks. In addition, you will have access to 18 virtual switches and 4 virtual buttons that you can use in your design and that you will see when interacting with the real hardware. This way, you will be able to turn on and off the switches or press the buttons and see how your design behaves. The boards are located in different universities, as you will see when using each board.

In this laboratory, you do not need any software or hardware installed in your computer, tablet or phone.

Summary

This lab gives students remote access to a real Terasic DE1-SoC board running the FPGAcademy DE1-SoC Computer with Nios V system. The FPGA bitstream is fixed by LabsLand, so students focus on building or uploading ELF programs for the Nios V RISC-V soft-core processor and observing the result on the live board.

Ways to use the lab

• Nios V for DE1-SoC: upload an existing ELF program and run it on the fixed Nios V system.
• Nios V C IDE for DE1-SoC: write C code in CodeIDE, build a Nios V ELF, and upload it to the board.
• Nios V Assembly IDE for DE1-SoC: write RISC-V assembly in CodeIDE, build a Nios V ELF, and upload it to the board.

Good fit for courses and activities

The lab is useful for introductory and intermediate activities in embedded systems, RISC-V assembly, embedded C, memory-mapped I/O, GPIO programming, JTAG UART output, and soft-core processor workflows on FPGA hardware. Typical exercises include printing messages over the JTAG UART, reading switch inputs, driving LEDs, comparing C and assembly implementations, and uploading instructor-provided ELF binaries.

Hardware and fixed system

The physical target is a Terasic DE1-SoC board with an Intel/Altera Cyclone V SoC FPGA. LabsLand programs the board with the FPGAcademy DE1-SoC Computer with Nios V bitstream before the student ELF is loaded. In this MVP, students do not change the FPGA fabric or upload a custom SOF from these entries; they run firmware on the provided Nios V system.

Switch and LED mapping

The on-screen controls are labelled NSW0 through NSW9. These are logical Nios V switches mapped to the GPIO/JP1 input path used by the fixed FPGAcademy system. The starter and demo programs mirror NSW0..NSW9 to LEDR0..LEDR9, so students can verify their program with the real board camera. The NSW naming is intentional because this Nios V system uses a different remote-control mapping from the generic HDL-mode switch labels.

References

For the processor system, memory map, and I/O details, see the FPGAcademy DE1-SoC Computer with Nios V reference. The lab documentation panel also links this reference from inside each session.