{"id":658,"date":"2026-10-11T16:05:22","date_gmt":"2026-10-11T16:05:22","guid":{"rendered":"https:\/\/labsland.com\/blog\/en\/?p=658"},"modified":"2026-10-11T16:47:02","modified_gmt":"2026-10-11T16:47:02","slug":"first-remote-fpga-assignment-verilog","status":"publish","type":"post","link":"https:\/\/labsland.com\/blog\/en\/2026\/10\/11\/first-remote-fpga-assignment-verilog\/","title":{"rendered":"A first remote FPGA assignment in Verilog: from requirement to truth table"},"content":{"rendered":"<style>#post-658 > .thumbnail,#post-658 > .entry-header{display:none}#post-658 .entry-content{max-width:850px;margin:0 auto}#post-658 > .meta{max-width:850px;margin:0 auto 24px}.ll-teaching-guide{font-size:18px;line-height:1.7;color:#18313e}.ll-teaching-guide h1{font-size:clamp(30px,4vw,46px);line-height:1.16;letter-spacing:-.025em;margin:0 0 26px}.ll-teaching-guide h2{font-size:27px;line-height:1.3;margin:46px 0 18px}.ll-teaching-guide h3{font-size:21px;margin:28px 0 12px}.ll-teaching-guide p{margin:0 0 20px}.ll-teaching-guide .lead{font-size:21px;line-height:1.6}.ll-teaching-guide .kicker{font-size:13px;font-weight:700;letter-spacing:.1em;text-transform:uppercase;color:#007681}.ll-teaching-guide .note,.ll-teaching-guide .downloads{padding:22px 24px;background:#edf5f3;border-left:4px solid #007681;margin:28px 0}.ll-teaching-guide .downloads p:last-child{margin-bottom:0}.ll-teaching-guide blockquote{border-left:4px solid #007681;background:#f4f7f6;padding:20px 24px;margin:28px 0;font-size:18px;font-style:normal}.ll-teaching-guide figure{margin:30px auto}.ll-teaching-guide figure img{display:block;width:auto;max-width:100%;height:auto;margin:0 auto}.ll-teaching-guide figure.product img{max-height:420px;width:auto}.ll-teaching-guide figcaption{font-size:14px;line-height:1.6;color:#48616e;margin-top:12px}.ll-teaching-guide table{border-collapse:collapse;width:100%;font-size:15px;line-height:1.5;margin:0}.ll-teaching-guide th,.ll-teaching-guide td{padding:12px 10px;vertical-align:top;text-align:left;border-bottom:1px solid #c6d4d8}.ll-teaching-guide th{background:#edf5f3;color:#18313e;font-weight:700;text-transform:none;letter-spacing:0}.ll-teaching-guide .table-wrap{max-width:100%;overflow-x:auto;margin:24px 0}.ll-teaching-guide .rubric{min-width:760px;font-size:14px}.ll-teaching-guide pre{max-width:100%;overflow:auto;padding:20px;background:#142c39;color:#f1f6f7;line-height:1.65;font-size:14px;border-radius:4px;white-space:pre}.ll-teaching-guide code{font-family:ui-monospace,monospace;font-size:.9em;background:transparent;overflow-wrap:anywhere}.ll-teaching-guide pre code{font-size:inherit;white-space:pre;overflow-wrap:normal;color:inherit}.ll-teaching-guide li{margin:10px 0}.ll-teaching-guide a{text-decoration:underline;text-underline-offset:3px;color:#006e78}.ll-teaching-guide a:focus-visible{outline:3px solid #ca7139;outline-offset:3px}@media(max-width:600px){.ll-teaching-guide{font-size:17px}.ll-teaching-guide h2{font-size:24px}.ll-teaching-guide .lead{font-size:19px}.ll-teaching-guide .note,.ll-teaching-guide .downloads{padding:18px}.ll-teaching-guide pre{font-size:12px;padding:14px}}.ll-teaching-guide .ll-language-nav{font-size:14px;margin:0 0 24px;padding:10px 0;border-bottom:1px solid #d4e1e3}.ll-language-nav a{font-weight:600}<\/style><div class=\"ll-teaching-guide\"><nav class=\"ll-language-nav\" aria-label=\"Article language\"><span aria-current=\"true\">English<\/span> \u00b7 <a href=\"https:\/\/labsland.com\/blog\/es\/2026\/10\/11\/primera-practica-fpga-remota-verilog\/\" lang=\"es\" hreflang=\"es\">Leer en espa\u00f1ol<\/a><\/nav><p class=\"kicker\">Digital design \u00b7 Teaching guide<\/p><h1>A first remote FPGA assignment in Verilog: from requirement to truth table<\/h1>\n<p class=\"lead\">A useful first FPGA assignment should end with more than a glowing LED. Ask students to turn a written requirement into a circuit, test every input combination and explain how their observations support their design.<\/p>\n<p>This guide uses a three-input access rule on a real remote DE1-SoC FPGA. It is small enough to inspect completely, and it comes with a plausible wrong answer that passes a casual \u201cthe light turns on\u201d check. You can use the student worksheet directly and keep the reference solution for feedback.<\/p>\n<div class=\"note\"><strong>At a glance.<\/strong> Introductory undergraduate digital design; familiarity with AND, OR and binary truth tables. Plan about 60 minutes of class work plus access and synthesis time. Students need a browser and access to the DE1-SoC Verilog lab.<\/div>\n<h2>Set up the DE1-SoC Verilog profile<\/h2>\n<p>The <a href=\"https:\/\/labsland.com\/en\/labs\/fpga-de1-soc\/\">DE1-SoC laboratory<\/a> provides browser-based design tools, virtual input controls and a camera view of the physical board. For this assignment, use the DE1-SoC Verilog profile described in the <a href=\"https:\/\/teach.labsland.com\/en\/lessons\/digital-logic-on-the-de1-soc-1-6-your-first-gates-on-real-hardware\/\">first-gates Teach lesson<\/a>: the file and top-level module are <code>leds_mirror.v<\/code> and <code>leds_mirror<\/code>, with <code>SW<\/code> inputs and <code>LEDR<\/code> outputs.<\/p>\n\n<figure class=\"product\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/de1-soc.jpg\" width=\"700\" height=\"573\" alt=\"Terasic DE1-SoC board, with the FPGA in the center and switches, buttons, LEDs and seven-segment displays along the lower edge.\"><figcaption>The Terasic DE1-SoC board used in the LabsLand laboratory.<\/figcaption><\/figure>\n<p>Before class, open the lab the way your students will and check the switch controls, camera view and where students will submit their work. Give students the worksheet and marking criteria before they start. If they are learning VHDL, the same requirement and truth table work with the <a href=\"https:\/\/teach.labsland.com\/en\/lessons\/digital-logic-on-the-de1-soc-with-vhdl-1-6-your-first-gates-on-real-hardware\/\">VHDL first-gates lesson<\/a>; the complete code supplied here is the Verilog version.<\/p>\n<h2>1. Start with a requirement students can challenge<\/h2>\n<blockquote>A teaching circuit has an enable input, E, and two permission inputs, A and B. Its indicator Y must turn on only when E is on and at least one permission is on. If E is off, Y must stay off, regardless of A and B.<\/blockquote>\n<p>Map E to <code>SW[2]<\/code>, A to <code>SW[1]<\/code>, B to <code>SW[0]<\/code>, and Y to <code>LEDR[0]<\/code>. There is no stored state and no clock: the output depends on the current inputs.<\/p>\n<p>Give students ten minutes to complete the eight-row truth table before showing code. Ask them to explain why E = 0 makes four different rows share the same output. Then ask which rows show that permission alone is insufficient.<\/p>\n<figure><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/fpga-rule.png\" width=\"480\" height=\"550\" alt=\"Illustrative logic diagram: permission A or permission B feeds an AND operation with enable E. The result is Y. E, A and B also appear on diagnostic LEDs 3, 2 and 1.\"><figcaption>Illustrative logic diagram. LEDs 3, 2 and 1 mirror E, A and B in the same order as the switches.<\/figcaption><\/figure>\n<p><strong>Teacher key:<\/strong> the expression is <code>Y = E AND (A OR B)<\/code>. Only rows 101, 110 and 111 should light Y when the input order is E, A, B.<\/p>\n<div class=\"table-wrap\"><table ><thead><tr><th scope=\"col\">E \u00b7 SW2<\/th><th scope=\"col\">A \u00b7 SW1<\/th><th scope=\"col\">B \u00b7 SW0<\/th><th scope=\"col\">Expected Y \u00b7 LEDR0<\/th><\/tr><\/thead><tbody><tr><td>0<\/td><td>0<\/td><td>0<\/td><td>0<\/td><\/tr><tr><td>0<\/td><td>0<\/td><td>1<\/td><td>0<\/td><\/tr><tr><td>0<\/td><td>1<\/td><td>0<\/td><td>0<\/td><\/tr><tr><td>0<\/td><td>1<\/td><td>1<\/td><td>0<\/td><\/tr><tr><td>1<\/td><td>0<\/td><td>0<\/td><td>0<\/td><\/tr><tr><td>1<\/td><td>0<\/td><td>1<\/td><td>1<\/td><\/tr><tr><td>1<\/td><td>1<\/td><td>0<\/td><td>1<\/td><\/tr><tr><td>1<\/td><td>1<\/td><td>1<\/td><td>1<\/td><\/tr><\/tbody><\/table><\/div>\n<h2>2. Implement the rule and make the inputs visible<\/h2>\n<p>Ask students to fill in the output expression in the <a href=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/fpga-student-starter.pdf\" download>student starter (PDF)<\/a>. The starter deliberately holds Y off, so successful compilation alone cannot complete the assignment.<\/p>\n<p>The reference below uses continuous assignments. <code>&amp;<\/code> and <code>|<\/code> are bitwise AND and OR; here each operand is one bit. The other three assigned LEDs mirror E, A and B. They are diagnostic outputs, not additional permission rules. All unused LEDs are explicitly driven off.<\/p>\n<pre><code>\/\/ Reference solution: E = SW[2], A = SW[1], B = SW[0].\n\/\/ DE1-SoC Verilog Teach profile: keep file\/module name leds_mirror.\nmodule leds_mirror(input [9:0] SW, output [9:0] LEDR);\n  assign LEDR[0] = SW[2] &amp; (SW[1] | SW[0]);\n  assign LEDR[3:1] = SW[2:0]; \/\/ E, A, B in switch order\n  assign LEDR[9:4] = 6&#x27;b000000;\nendmodule\n<\/code><\/pre>\n<p>The reference solution is public, so a correct implementation alone is not evidence of independent work. Ask students to justify the assignments, record their own observations and explain a test that exposes the faulty rule.<\/p>\n<h2>3. Build, upload and record all eight rows<\/h2>\n<p>Use <strong>Synthesize<\/strong>, resolve build errors, then select <strong>Upload to FPGA<\/strong>. Synthesis alone does not program the board. After every edit, synthesize and upload again before recording new observations.<\/p>\n<ol><li>Set all switches off. Confirm the diagnostic LEDs agree with E = A = B = 0.<\/li><li>Set <em>all three<\/em> relevant switches explicitly for each row, in the order 000, 001, 010, 011, 100, 101, 110, 111. Avoid instructions such as \u201cthen turn A on\u201d that leave the previous B state ambiguous.<\/li><li>Allow the camera view to settle. Record the observed Y value separately from the prediction. In this profile, the LEDs are active-high: lit means 1.<\/li><li>For any mismatch, record the row, the code version and what you checked. Keep the original observation when you correct a transcription or implementation error.<\/li><li>After the main table, vary an unused switch while holding E, A and B fixed. Explain why Y should not change.<\/li><\/ol>\n<p>With a correct design, Y stays off for the first five rows and lights for the last three. Record the stable LED states from the camera; this exercise does not measure switching speed.<\/p>\n<h2>4. Use one wrong expression to teach useful testing<\/h2>\n<p>Now show <code>Y = (E AND A) OR B<\/code>. Before anyone edits code, ask for a row where the two rules disagree. There are exactly two: EAB = 001 and 011. In both, B turns Y on while E is off, so B has bypassed the enable. The other six rows give the same output for both rules, including 111. A demonstration that only checks \u201ceverything on\u201d cannot catch this mistake.<\/p>\n<p>Students can explain this on paper or test the faulty expression, clearly labeling that run. If they upload it, they must restore their correct design and repeat the verification. A useful exit question is: \u201cIf you could run only one test to catch this error, which row would you choose, and why would 111 be a poor choice?\u201d<\/p>\n<h2>5. Assess the evidence, not the screenshot alone<\/h2>\n<p>Request one compact submission: the final source file, the eight predicted and observed rows, two labeled camera captures: EAB = 001, plus one row assigned by the teacher from 101, 110 and 111, and a short explanation of the counterexample. The captions should identify switch settings, Y, the diagnostic LEDs and the code version. One capture with a lit LED cannot demonstrate the whole truth table.<\/p>\n<div class=\"table-wrap\"><table ><thead><tr><th scope=\"col\">Criterion<\/th><th scope=\"col\">Points<\/th><th scope=\"col\">What earns full credit<\/th><\/tr><\/thead><tbody><tr><td>Requirement and prediction<\/td><td>4<\/td><td>All eight predictions correct; the explanation distinguishes enable from permission.<\/td><\/tr><tr><td>Implementation<\/td><td>4<\/td><td>The expression implements the requirement; all outputs are defined and the input mapping is consistent.<\/td><\/tr><tr><td>Hardware evidence<\/td><td>4<\/td><td>Eight observed rows are recorded; the two captures support their labeled rows; any mismatch is documented.<\/td><\/tr><tr><td>Reasoning and debugging<\/td><td>4<\/td><td>The student explains why 001 or 011 exposes the faulty rule and why 111 does not.<\/td><\/tr><\/tbody><\/table><\/div>\n<p>For each criterion, award 3 for a minor omission, 2 for a substantial but incomplete attempt, 1 for minimal relevant evidence and 0 for no evidence. Publish this 16-point scheme with the worksheet. If access fails, allow the prediction, code and debugging explanation to be submitted first; leave the hardware evidence pending rather than asking students to invent it.<\/p>\n<h2>Common mistakes worth discussing<\/h2>\n<ul><li><strong>Reversing the input order.<\/strong> The table is EAB, which is SW2\u2013SW1\u2013SW0. Use the diagnostic LEDs to check the mapping.<\/li><li><strong>Testing an older upload.<\/strong> A new source file does not change the running circuit until the new build is uploaded.<\/li><li><strong>Treating compilation as correctness.<\/strong> Both the starter and the faulty expression can compile. The truth table tests the requirement.<\/li><li><strong>Using pushbuttons instead of switches.<\/strong> The documented DE1-SoC buttons have different polarity. This exercise deliberately uses switches only.<\/li><li><strong>Reporting expectations as observations.<\/strong> Keep the worksheet\u2019s two columns separate, including when the camera is unreadable.<\/li><\/ul>\n<div class=\"downloads\"><strong>Use this assignment<\/strong><p><a href=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/fpga-student-worksheet.pdf\">Download the student worksheet (PDF)<\/a> \u00b7 <a href=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/fpga-student-starter.pdf\" download>Download starter (PDF)<\/a> \u00b7 <a href=\"https:\/\/labsland.com\/blog\/en\/wp-content\/uploads\/sites\/2\/2026\/10\/fpga-reference-and-test.pdf\" download>Download reference and test (PDF)<\/a><\/p><p>The reference was simulated with Icarus Verilog across all 1,024 switch settings. It has not been verified in a physical-board run.<\/p><\/div>\n<h2>Where to go next<\/h2>\n<p>For a guided introduction before this task, start with the <a href=\"https:\/\/teach.labsland.com\/en\/lessons\/digital-logic-on-the-de1-soc-1-6-your-first-gates-on-real-hardware\/\">Verilog first-gates lesson in Teach<\/a>. Once students can connect a requirement, implementation and test, move to the <a href=\"https:\/\/teach.labsland.com\/en\/lessons\/digital-logic-on-the-de1-soc-2-6-truth-tables-sop-pos-k-maps-and-a-multiplexer\/\">truth-table and minimization lesson<\/a>. Preview the lessons publicly, then sign in with your educator account to prepare a class session and check your lab access.<\/p>\n<\/div>","protected":false},"excerpt":{"rendered":"<p>Teach a first Verilog assignment on a remote DE1-SoC FPGA with a truth table, simulation-checked code, a student worksheet and a practical marking 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